library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lcd_decode is
port 
(
sech,secl:in integer range 0 to 9;
sech_decode,secl_decode:out std_logic_vector(7 downto 0)
);
end lcd_decode;
architecture behav of lcd_decode is
begin 
	decode:process(sech,secl)
	begin 
		case sech is
		when 0=>sech_decode<=X"30";
		when 1=>sech_decode<=X"31";
		when 2=>sech_decode<=X"32";
		when 3=>sech_decode<=X"33";
		when 4=>sech_decode<=X"34";
		when 5=>sech_decode<=X"35";
		when 6=>sech_decode<=X"36";
		when 7=>sech_decode<=X"37";
		when 8=>sech_decode<=X"38";
		when 9=>sech_decode<=X"39";
		end case;
		case secl is
		when 0=>secl_decode<=X"30";
		when 1=>secl_decode<=X"31";
		when 2=>secl_decode<=X"32";
		when 3=>secl_decode<=X"33";
		when 4=>secl_decode<=X"34";
		when 5=>secl_decode<=X"35";
		when 6=>secl_decode<=X"36";
		when 7=>secl_decode<=X"37";
		when 8=>secl_decode<=X"38";
		when 9=>secl_decode<=X"39";
		end case;
	end process;
end behav;